The present invention relates to a method for manufacturing a flat panel display. More particularly, the present invention is directed to a method for manufacturing a liquid crystal display (LCD) having a gate insulating film with a high dielectric constant and excellent leakage characteristics.
As a next-generation display device intended to replace cathode ray tubes (CRTs), liquid crystal displays (LCDs) have been developed in parallel with the technological advancements in portable computers, office automation equipment and workstations, and high definition televisions. Such LCDs can have either a simple matrix form or an active matrix form which utilize the electro-optic properties of a liquid crystal, whose molecular arrangement is varied according to an applied electric field. Specifically, active-matrix LCDs utilize a combination of liquid crystal technology and semiconductor technology, and are recognized as being generally superior to CRT displays.
As LCDs achieve higher definition and wide-screen capabilities, more gate lines and a smaller pixel area inevitably reduces line width, thereby slowing the gate response time. To improve this situation, there is a technique which uses a low-resistance metal (e.g., aluminum) as the gate line, and then uses anodic oxidation to form a gate insulating film.
FIG. 1 shows a plan layout diagram of a conventional liquid crystal display. FIG. 2A to FIG. 2D are sectional views showing a liquid crystal display having an aluminum gate line and a double gate insulating film structure. In more detail, FIG. 2A is a sectional view taken along line I-I' of FIG. 1, showing a wiring matrix portion, FIG. 2B is a sectional view taken along line II-II' of FIG. 1, showing a thin film transistor (TFT) portion, FIG. 2C is a sectional view taken along line III-III' of FIG. 1, showing an additional capacitor portion, and FIG. 2D is a sectional view showing a terminal portion (not shown in FIG. 1).
As shown in FIG. 1 and FIG. 2A to FIG. 2D, an aluminum film is formed to a thickness of approximately 1,000 to 2,000 A on a substrate 10 by a sputter deposition method. Then, the aluminum is patterned so that a gate wiring 20 (FIG. 2A), a gate electrode 30 (FIG. 2B), a first additional capacity electrode 40 (FIG. 2C), and an electrode of terminal portion 50 (FIG. 2D) can be formed by the aluminum film. Then, a photoresist (not shown) is coated to a thickness of 3 .mu.m, and portions of the photoresist formed on a wiring matrix portion A, on a TFT portion B and on an additional capacitor portion C (defined by dotted lines in FIG. 1) are removed by a photoetching process so as to expose these areas. Then, substrate 10 having the patterned aluminum formed thereon is dipped into an anodic oxidation solution, and a voltage of approximately 60 V to 80 V is supplied to the exposed aluminum layer for 30 minutes. Thus, an aluminum oxide (Al.sub.2 O.sub.3) film 14 having a thickness of approximately 1,000 to 2,000 A is formed on the surface of the gate wiring 20 (FIG. 2A), the gate electrode 30 (FIG. 2B) and the first additional capacity electrode 40 (FIG. 2C). In other words, the aluminum layer exposed in regions A, B and C of FIG. 1 is partially and anodically oxidized.
Then, the photoresist is removed, and the resultant structure is heated to 200.degree. to 400.degree. C. for 60 minutes under atmospheric or vacuum conditions. Then, first silicon nitride layer 16 is formed on the Al.sub.2 O.sub.3 film 14 to a thickness of 1,000 to 3,000 A by a chemical vapor deposition (CVD) method, and a first amorphous silicon layer 18 is formed to a thickness of 200 to 1,000 A thereon. Sequentially, a second nitride silicon layer 22 is formed to a thickness of 1,000 to 2,000 A on the first amorphous silicon layer 18. Then, the second nitride silicon layer 22 is patterned to form a second nitride silicon pattern 22 only on the channel of the TFT. Then, a second amorphous silicon layer 24 doped with phosphorous is formed to a thickness of 200 to 500 A on the first amorphous silicon layer 18 and the second nitride silicon pattern 22. Then, the second amorphous silicon layer 24 and the first amorphous silicon layer 18 are patterned to form simultaneously a second amorphous silicon pattern 24 and a first amorphous silicon pattern 18 under the source and drain regions of the TFT portion, as shown in FIG. 2B.
Then, chromium (Cr) and aluminum (Al) are sequentially deposited by a sputter deposition method to a thickness of 500 to 1,000 A and 3,000 to 8,000 A, respectively, and patterned so as to form a signal line 28, TFT source/drain electrodes 26 (FIG. 2B), and a terminal 26' and 28' (FIG. 2D). Then, a transparent electrode of indium-tin oxide (ITO) is formed to a thickness of approximately 1,000 A by a sputter deposition method and patterned, to thereby form a pixel electrode 32 (FIGS. 2A & 2B), an additional capacitor electrode 42 (FIG. 2C) and a pad terminal pattern 52 (FIG. 2D).
In the conventional method, anodic oxidation is performed using a solution of tartaric acid and an ethylene glycol or a solution of tartaric acid and propylene glycol. A heat treatment process is performed under atmospheric or vacuum conditions at 200.degree. to 400.degree. C. for 60 minutes after the anodic oxidization, and Al-3% Si or Al-0.3% Pd is used for gate wiring. In the conventional method, the double insulating layer structure of Al.sub.2 O.sub.3 /SiNx is used as a gate insulating film. Therefore, hillocks will not be generated on the surface of an aluminum and the insulating characteristic of the Al.sub.2 O.sub.3 film can be thereby improved.
However, the gate line may be disconnected due to defects in the aluminum material and short circuiting among layers may occur due to the hillock growth caused by the heating process of a subsequent procedure, which lowers the yield.
In addition, the gate wiring and pad terminal patterns cannot be simultaneously formed due to the softness of the aluminum material and due to electro-chemical etching between the ITO film and the aluminum. Therefore, a chromium pad needs to be inserted between the aluminum film and gate wiring, which complicates the manufacturing process.
Moreover, since Al.sub.2 O.sub.3 /SiNx has to be used as a dielectric film of an additional or accumulated capacitor, leakage current and the dielectric constant are low compared with a case where a material such as Ta.sub.2 O.sub.5 /SiNx having a high dielectric constant is used. Therefore, the area of the additional or accumulated capacitor has to be increased in order to ensure the same capacitance, which may reduce the aperture ratio.